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Home  › COX SPI Peripheral Interface

COX SPI Peripheral Interface

Version: 1.00 - 13. June 2010

Contents

Overview

SPI peripheral is the master device on SPI bus, it selects a slave device to start data transfer. It contains three signals : serial clock (SCK, output), serial data in (MISO, input), serial data out (MOSI, output).

SPI peripheral can operate one or more slave devices and use chip select signal (SS) to select desired slave device.

Interface Definition

SPI Interface Definition : A COX SPI Interface is a structure variable of COX_SPI_PI type, it contains a list of pointers to the functions that implement the standard functions specified by COX. COX defined SPI standard functions used to setup the SPI peripheral and start data transfer. Use different variables to access different SPI Master peripherals.

SPI Master Interface 
typedef struct {
  COX_Status (*Init)      (uint8_t mode,  uint32_t rate);      
  uint32_t   (*Write)     (const void *wbuf, uint32_t wlen);
  uint32_t   (*Read)      (void *rbuf, uint32_t rlen);
  uint32_t   (*ReadWrite) (uint32_t wdat);  
  COX_Status (*Cfg)       (uint8_t index, uint32_t arg, uint32_t *pre_arg);  
} COX_SPI_PI_Def;
typedef const COX_SPI_PI_Def COX_SPI_PI;
Member 
COX_Status (*Init)      (uint8_t mode,  uint32_t rate); 
/* Initializes the SPI  peripheral */ 
uint32_t   (*Write)     (const void *wbuf, uint32_t wlen); 
/* Send a block of data */
uint32_t   (*Read)      (void *rbuf,    uint32_t rlen);
/* Receive a block of data */
uint32_t   (*ReadWrite) (uint32_t wdat);
/* Read write data */	
COX_Status (*Cfg)       (uint8_t index, uint32_t arg, uint32_t *pre_arg);
/* Configure the peripheral */


Global Define

Name Description
COX_SPI_CFG_MODE SPI mode
COX_SPI_CFG_RATE
 Serial clock rate
COX_SPI_CFG_BITS
 Number of data bits
COX_SPI_CFG_FSB
 Data transfer order
COX_SPI_MODE0 SPI Mode 0 ( CPOL = 0, CPHA = 0 )
COX_SPI_MODE1 SPI Mode 1 ( CPOL = 0, CPHA = 1 )
COX_SPI_MODE2 SPI Mode 2 ( CPOL = 1, CPHA = 0 )
COX_SPI_MODE3 SPI Mode 3 ( CPOL = 1, CPHA = 1 )
COX_SPI_FSB_MSB MSB first sent
COX_SPI_FSB_LSB LSB first sent

Standard Function

Name Description
Init Initializes the SPI Master peripheral
Write Send a block of data
Read Receive a block of data
ReadWrite Read write a data
Cfg Configure the peripheral

COX_Status Init (uint8_t mode, uint32_t rate)
Description Initializes the SPI peripheral

Parameter

mode : SPI mode, should be

  • COX_SPI_MODE0 : SPI Mode 0 ( CPOL = 0, CPHA = 0 )
  • COX_SPI_MODE1 : SPI Mode 1 ( CPOL = 0, CPHA = 1 )
  • COX_SPI_MODE2 : SPI Mode 2 ( CPOL = 1, CPHA = 0 )
  • COX_SPI_MODE3 : SPI Mode 3 ( CPOL = 1, CPHA = 1 )

rate : Clock rate,in Hz
>Return Code COX_SUCCESS or COX_ERROR
uint32_t Write (void *wbuf, uint32_t wlen)
Description Send a block of data
Parameter

wbuf : Pointer to transmit buffer

wlen : Length of transmit buffer
Return Code Length of data sent
uint32_t Read (void *rbuf, uint32_t rlen)
Description Receive a block of data
Parameter

rbuf : Pointer to receive buffer

rlen : Length of receive buffer
Return Code Length of data received
uint32_t ReadWrite (uint32_t wdat)
Description Read write a data
Parameter wdat : Send data
Return Code Data received
COX_Status Cfg (uint8_t index, uint32_t arg, uint32_t *pre_arg)
Description Cofigure SPI Master peripheral
Parameter

spi : Specify the SPI peripheral

index : Configuration index, should be :

  • COX_SPI_CFG_MODE : Set spi mode， arg should be
    • COX_SPI_MODE0 : SPI Mode 0 ( CPOL = 0, CPHA = 0 )
    • COX_SPI_MODE1 : SPI Mode 1 ( CPOL = 0, CPHA = 1 )
    • COX_SPI_MODE2 : SPI Mode 2 ( CPOL = 1, CPHA = 0 )
    • COX_SPI_MODE3 : SPI Mode 3 ( CPOL = 1, CPHA = 1 )
  • COX_SPI_CFG_RATE : Set serial clock rate
  • COX_SPI_CFG_BITS : Set number of data bits
  • COX_SPI_CFG_FSB : Set data transfer order， arg should be
    • COX_SPI_FSB_MSB : MSB first sent
    • COX_SPI_FSB_LSB : LSB first sent

arg : Configuration argument

pre_arg : Return previous configuration argument
Return Code COX_SUCCESS or COX_ERROR

Available Interface

Vendor Chip Interface Description
NXP LPC17xx Series pi_spi0 SPI Master Interface based on SSP0
pi_spi1 SPI Master Interface based on SSP1

 
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